SLL's embedded software innovation has been recognised by our customers and partners. Major FPGA, memory, and development board makers now officially partner with SLL. This ensures SLL IP is validated on a wide range of physical devices. SLL customers are located in most geographical regions, and include Fortune Global 500's, government agencies, and SME's from USA and Canada to China.
Intel FPGA Design Services
For faster, smaller and more capable designs
SLL brings a wide range of expertise and proprietary tools to help you reduce the area and increase the performance and capabilities of your Intel FPGA design. Some examples of how we achieve these goals are provided below.
We employ optimised Qsys components for far superior results. One example is our professional grade Avalon / Merlin Protocol Interconnects.
- Every Intel FPGA design uses Avalon / Merlin Interconnects
- SLL offers Qsys components that replace several of the modules in the Avalon / Merlin interconnect, to deliver far superior results
- up to 36% circuit area savings and 40% faster clock speeds
So you can consume less of your hardware resources on interconnect logic, and allocate them to capabilities that add value to your design!
KEY BENEFITS FOR ALL AVALON / MERLIN INTERCONNECTS
Take greater control of your interconnect
- Supports multiple types of arbitration and pipelining implementations
- Permits rapid “what if” design space exploration, to find optimal configurations for your design
Reduces interconnect circuit area up to 36% in the main functions
Increases clock speeds up to 40%
- Every time there is a N master to 1 target arbiter
- Every time there is a burst capable interconnect
- Every time there is a pipeline stage in low area configurations
Static time sign off is easier and faster
- Due to shorter critical path and more precise fine grain pipelining
SAVES RESOURCES, REDUCES PROJECT DEVELOPMENT TIME AND HARDWARE COSTS, INCREASES YOUR INTERCONNECT PERFORMANCE:
DELIVERS BETTER RESULTS FOR LESS HARDWARE RESOURCES
Suitable for all Intel FPGA’s. including low speed, low cost FPGA’s.
Enables the critical path through the interconnect to easily exceed 150 MHz
Full Qsys and NIOS II support
- no special development tools needed
Overcomes the limitations of Qsys and the Avalon / Merlin interconnect
- Intel’s interconnect is instantiated by Qsys in every design
- Intels interconnect circuit area can be high
- Intel interconnect frequency can be low, and this is often a limiter for the top clock speed of the entire Qsys project!
- Low clock speed negatively impacts static timing sign off and place and route, increasing project costs and reducing final results
SLL solutions upgrade the Avalon / Merlin interconnect to give you greater configurability and control over this most important part of every Intel FPGA project – to enable far superior results.
- Suitable for all Intel FPGA families including low end device variants
- Processor and peripheral agnostic
- Use with hard processor cores in Intel SoC FPGA’s
- Use with any type of soft processor eg Nios II / f and /e
- Use with any type of peripherals eg co-procesors, communications, etc
- Full automated support in Qsys for:
- the entire range of Intel Avalon protocol variants
- Avalon – to -AXI bridging